The present invention relates to a semiconductor device and a method for fabricating the same, more specifically, a semiconductor device including an inter-layer insulating film of a low dielectric constant material and a method for fabricating the semiconductor device.
In semiconductor device fabrication processes, a number of elements are formed on one semiconductor wafer, and the semiconductor wafer is cut along dicing lines into discrete LSI chips. On the side walls along the dicing lines, the interfaces of many inter-layer insulating films laid in the process of forming the elements are exposed. The interfaces are often paths for water intrusion, causing problems, such as erroneous operations and breakages, etc. of semiconductor devices, which impair their reliability. Stresses in the dicing, and stresses, etc. due to thermal expansion coefficient differences between the inter-layer insulating films and a sealing resin cause cracks in the inter-layer insulating films, and the cracks often are paths for water intrusion.
A structure bounding each LSI chip is provided inside the dicing lines along all the border, whereby the intrusion of water through the interfaces of the inter-layer insulating films and the extension of cracks in the inter-layer insulating films into the chip are prevented. Such structure is formed of layers of dummy patterns which are formed of the same layers as the interconnection layers forming the internal circuits and is often called a guard ring, a seal ring, a moisture resistant ring or others. Structures for preventing the water intrusion and cracks are described in, e.g., Japanese published unexamined patent application No. 2000-232081, Japanese published unexamined patent application No. 2000-232104, Japanese published unexamined patent application No. 2000-232105, Japanese published unexamined patent application No. 2000-277465, Japanese published unexamined patent application No. 2000-277713, Japanese published unexamined patent application No. 2001-053148, Japanese published unexamined patent application No. 2001-168093, and Japanese published unexamined patent application No. 2002-134506.
On the other hand, as semiconductor devices are larger scaled and more highly integrated, the design rules for the interconnection have been diminished as the generations have passed. Conventionally, the interconnection layers have been formed by depositing conducting materials and patterning the deposited conducting materials by lithography and dry etching, but as the generation passes, it has technical limits. As a new forming process which takes the place of the conventional interconnection layer forming process, the so-called damascene process, in which groove patterns and hole patterns are formed in inter-layer insulating films, and conducting materials are buried in the grooves and the holes, is increasingly used. The damascene process can form interconnection layers of low resistance materials, such as copper which is difficult for reactive etching, and is very effective to form low-resistance interconnection layers having micronized patterns.
As the interconnection layers are more micronized, the spacings of interconnections are smaller. Increase of the parasitic capacitance formed via the inter-layer insulating films is one factor for hindering speed-up of semiconductor devices. The use of organic insulating materials having lower dielectric constants (low-kmaterials) than the conventionally used silicon oxide film and silicon nitride film are studied. As the organic insulating materials, an organic-based polymer called “SiLK” (registered trademark) from The Dow Chemical Company, which is an organic SOG material, an organic-based polymer called “FLARE” (registered trade mark) from Honeywell Electronic Materials, etc. are known.
Low dielectric constant materials, such as the above-described organic insulating materials, etc. are largely different from the conventional materials having siloxane bonds, which are based on silicon oxide film in physical properties, such as Young's modulus, hardness and thermal expansion coefficient. Generally, to obtain low dielectric constant, structures, as of atoms or molecules, inside materials must be changed. The dielectric constant can be lowered as inter-atom distances or inter-molecule distances are larger, but increase of inter-atom distances or inter-molecule distances lead to lower bond strength. Accordingly, when a multi-level interconnection structure is formed of low dielectric constant materials, the adhesion in the interfaces with the inter-layer insulating films is lowered in comparison with the adhesion in the interfaces with the inter-layer insulating films of insulating materials based on the conventional silicon oxide film having siloxane bonds, and the mechanical strength of the inter-layer insulating films themselves is also lowered.
Accordingly, it has been found that the semiconductor device having the inter-layer insulating films formed of low dielectric constant materials have lower mechanical strength in comparison with the semiconductor device including the conventional insulating materials and has cracks and peelings due to even the mechanical stresses which have been insignificant in the fabrication process of the conventional structures.
In dual damascene process, for example, in the CMP (Chemical Mechanical Polishing) for planarizing inter-layer insulating films and filling copper interconnection layers, cracks and peelings have been often caused due to mechanical stresses applied to the interfaces between the inter-layer insulating films and inside the inter-layer insulating films.
On the guard rings, the inductors, etc., which are structures of stacked acutely bent interconnections, thermal stresses during processing and stresses from packages after mounted tend to be concentrated, often causing cracks from parts near the pattern corners to the inter-layer insulating films.
Due to wire bonding and formation of bumps, stresses are concentrated on the interconnection materials of pads, and the mechanical stresses often cause cracks in parts upper or lower of the pads.
In the fuse circuit regions of the redundant circuits, cracks are often caused due to thermal impulses of lasers when the metal fuses are cut by the lasers.
The cracks caused in the inter-layer insulating films do not impair device functions. However, the cracks are extended during use of devices, often causing serious problems in the reliability. To solve this problem, structures and fabrication methods which can effectively prevent the cracks and peelings in the semiconductor devices using low dielectric constant materials are expected.